Module Definition
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Module : adc_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.00 96.00

Source File(s) :
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.adc_ctrl_csr_assert 96.00 96.00


Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.00 96.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.00 96.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : adc_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 25 25 100.00 24 96.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 25 25 100.00 24 96.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 2147483647 0 0 0
adc_chn0_filter_ctl_0_rd_A 2147483647 2290 0 0
adc_chn0_filter_ctl_1_rd_A 2147483647 2399 0 0
adc_chn0_filter_ctl_2_rd_A 2147483647 2566 0 0
adc_chn0_filter_ctl_3_rd_A 2147483647 2233 0 0
adc_chn0_filter_ctl_4_rd_A 2147483647 2268 0 0
adc_chn0_filter_ctl_5_rd_A 2147483647 2443 0 0
adc_chn0_filter_ctl_6_rd_A 2147483647 2519 0 0
adc_chn0_filter_ctl_7_rd_A 2147483647 2265 0 0
adc_chn1_filter_ctl_0_rd_A 2147483647 2322 0 0
adc_chn1_filter_ctl_1_rd_A 2147483647 2372 0 0
adc_chn1_filter_ctl_2_rd_A 2147483647 2338 0 0
adc_chn1_filter_ctl_3_rd_A 2147483647 2426 0 0
adc_chn1_filter_ctl_4_rd_A 2147483647 2313 0 0
adc_chn1_filter_ctl_5_rd_A 2147483647 2465 0 0
adc_chn1_filter_ctl_6_rd_A 2147483647 2560 0 0
adc_chn1_filter_ctl_7_rd_A 2147483647 2338 0 0
adc_en_ctl_rd_A 2147483647 2071 0 0
adc_fsm_rst_rd_A 2147483647 1813 0 0
adc_intr_ctl_rd_A 2147483647 2434 0 0
adc_lp_sample_ctl_rd_A 2147483647 1900 0 0
adc_pd_ctl_rd_A 2147483647 2079 0 0
adc_sample_ctl_rd_A 2147483647 1789 0 0
adc_wakeup_ctl_rd_A 2147483647 2117 0 0
intr_enable_rd_A 2147483647 2555 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 0

adc_chn0_filter_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2290 0 0
T18 373473 33 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 22 0 0
T30 0 11 0 0
T31 0 13 0 0
T32 0 38 0 0
T33 0 36 0 0
T34 0 9 0 0
T35 0 14 0 0
T36 0 22 0 0
T37 0 20 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0

adc_chn0_filter_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2399 0 0
T18 373473 42 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 15 0 0
T30 0 29 0 0
T31 0 14 0 0
T32 0 37 0 0
T33 0 47 0 0
T34 0 3 0 0
T35 0 15 0 0
T36 0 31 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 11 0 0

adc_chn0_filter_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2566 0 0
T18 373473 24 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 10 0 0
T30 0 13 0 0
T31 0 31 0 0
T32 0 52 0 0
T33 0 34 0 0
T34 0 19 0 0
T35 0 20 0 0
T36 0 18 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 7 0 0

adc_chn0_filter_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2233 0 0
T18 373473 16 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 18 0 0
T30 0 21 0 0
T31 0 18 0 0
T32 0 18 0 0
T33 0 15 0 0
T34 0 4 0 0
T35 0 21 0 0
T36 0 26 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 21 0 0

adc_chn0_filter_ctl_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2268 0 0
T18 373473 40 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 10 0 0
T30 0 20 0 0
T31 0 20 0 0
T32 0 50 0 0
T33 0 41 0 0
T34 0 11 0 0
T35 0 25 0 0
T36 0 34 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 2 0 0

adc_chn0_filter_ctl_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2443 0 0
T18 373473 40 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 17 0 0
T30 0 27 0 0
T31 0 17 0 0
T32 0 49 0 0
T33 0 42 0 0
T34 0 4 0 0
T35 0 13 0 0
T36 0 24 0 0
T37 0 16 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0

adc_chn0_filter_ctl_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2519 0 0
T18 373473 33 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 19 0 0
T30 0 15 0 0
T31 0 9 0 0
T32 0 35 0 0
T33 0 44 0 0
T34 0 23 0 0
T35 0 16 0 0
T36 0 15 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 10 0 0

adc_chn0_filter_ctl_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2265 0 0
T18 373473 38 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 8 0 0
T30 0 15 0 0
T31 0 29 0 0
T32 0 43 0 0
T33 0 52 0 0
T34 0 14 0 0
T35 0 17 0 0
T36 0 14 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 14 0 0

adc_chn1_filter_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2322 0 0
T18 373473 45 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 12 0 0
T30 0 21 0 0
T31 0 31 0 0
T32 0 32 0 0
T33 0 36 0 0
T34 0 7 0 0
T35 0 18 0 0
T36 0 44 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 14 0 0

adc_chn1_filter_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2372 0 0
T18 373473 30 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 13 0 0
T30 0 36 0 0
T31 0 28 0 0
T32 0 48 0 0
T33 0 48 0 0
T34 0 15 0 0
T35 0 25 0 0
T36 0 19 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 9 0 0

adc_chn1_filter_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2338 0 0
T18 373473 31 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 9 0 0
T30 0 28 0 0
T31 0 22 0 0
T32 0 31 0 0
T33 0 38 0 0
T34 0 13 0 0
T35 0 10 0 0
T36 0 21 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 4 0 0

adc_chn1_filter_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2426 0 0
T18 373473 53 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 14 0 0
T30 0 33 0 0
T31 0 11 0 0
T32 0 30 0 0
T33 0 30 0 0
T34 0 18 0 0
T35 0 25 0 0
T36 0 17 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 6 0 0

adc_chn1_filter_ctl_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2313 0 0
T18 373473 43 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 5 0 0
T30 0 29 0 0
T31 0 22 0 0
T32 0 39 0 0
T33 0 44 0 0
T34 0 25 0 0
T35 0 21 0 0
T36 0 32 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 6 0 0

adc_chn1_filter_ctl_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2465 0 0
T18 373473 35 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 13 0 0
T30 0 21 0 0
T31 0 12 0 0
T32 0 35 0 0
T33 0 45 0 0
T34 0 13 0 0
T35 0 23 0 0
T36 0 29 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 8 0 0

adc_chn1_filter_ctl_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2560 0 0
T18 373473 38 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 8 0 0
T30 0 17 0 0
T31 0 19 0 0
T32 0 33 0 0
T33 0 58 0 0
T34 0 4 0 0
T35 0 19 0 0
T36 0 25 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 16 0 0

adc_chn1_filter_ctl_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2338 0 0
T18 373473 50 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 19 0 0
T30 0 29 0 0
T31 0 22 0 0
T32 0 42 0 0
T33 0 27 0 0
T34 0 2 0 0
T35 0 20 0 0
T36 0 23 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 7 0 0

adc_en_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2071 0 0
T18 373473 34 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 10 0 0
T30 0 17 0 0
T31 0 8 0 0
T32 0 28 0 0
T33 0 34 0 0
T34 0 20 0 0
T35 0 17 0 0
T36 0 13 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 5 0 0

adc_fsm_rst_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1813 0 0
T18 373473 35 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 12 0 0
T30 0 24 0 0
T31 0 15 0 0
T32 0 31 0 0
T33 0 33 0 0
T34 0 16 0 0
T35 0 19 0 0
T36 0 24 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 7 0 0

adc_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2434 0 0
T18 373473 24 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 16 0 0
T31 0 14 0 0
T32 0 39 0 0
T33 0 32 0 0
T34 0 16 0 0
T35 0 22 0 0
T36 0 22 0 0
T37 0 23 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 8 0 0

adc_lp_sample_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1900 0 0
T18 373473 31 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 9 0 0
T30 0 22 0 0
T31 0 18 0 0
T32 0 43 0 0
T33 0 44 0 0
T34 0 9 0 0
T35 0 16 0 0
T36 0 19 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 12 0 0

adc_pd_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2079 0 0
T18 373473 31 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 16 0 0
T30 0 15 0 0
T31 0 30 0 0
T32 0 39 0 0
T33 0 38 0 0
T34 0 14 0 0
T35 0 27 0 0
T36 0 22 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 6 0 0

adc_sample_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1789 0 0
T18 373473 41 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 10 0 0
T30 0 25 0 0
T31 0 11 0 0
T32 0 39 0 0
T33 0 45 0 0
T34 0 8 0 0
T35 0 19 0 0
T36 0 14 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 15 0 0

adc_wakeup_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2117 0 0
T18 373473 23 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 8 0 0
T30 0 21 0 0
T31 0 20 0 0
T32 0 45 0 0
T33 0 34 0 0
T34 0 10 0 0
T35 0 23 0 0
T36 0 17 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 14 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2555 0 0
T18 373473 29 0 0
T19 891355 0 0 0
T20 893450 0 0 0
T29 0 68 0 0
T30 0 58 0 0
T31 0 57 0 0
T32 0 74 0 0
T33 0 38 0 0
T38 24565 0 0 0
T39 584489 0 0 0
T40 277380 0 0 0
T41 648316 0 0 0
T42 418545 0 0 0
T43 710917 0 0 0
T44 28258 0 0 0
T45 0 7 0 0
T46 0 4 0 0
T47 0 28 0 0
T48 0 16 0 0

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